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ADDI7013 timing output?

Question asked by knkong0911 on Feb 2, 2016
Latest reply on Mar 4, 2016 by TFAnalog

Hi everyone,

 

We have tried to operate ADDI7013 and

found a problem that simulation result is not applied to device (ADDI7013).

 

Please advice to us to solve this problem.

And please recommend another new advanced part (or replacement of ADDI7013).

 

Please refer to attachment as below.

 

Thanks,

Kyungnam

 

-----------------------------------------------

The project information (@VisualTglde software) is as follwings. 

 

VisualTglde Project

----------------------------

 

ISATG Part = ADDI7013

 

CLK_Signal = HBLK1, HBLK2, RGBLK1, CLPOB, PBLK

 

Pattern Editor = toggle_vector(33:HBLK1)(c); toggle_vector(0:HBLK2,RGBLK1)(r);toggle_vector(1067:HBLK1)(r);toggle_vector(0:HBLK2,RGBLK1)(r); rts;

 

VD_POS1 = 0

VD_POS2 = 105

HD_POS1 = 0

HD_POS2 = 80

VDLEN_mode0_field0 = 2331000

HDLEN_mode0_field0 = 1125

 

Simulation result by using VisualTglde tool is OK!

But the device ADDI7013 signal (VD & HD, H1 & H2) output is not the timing output as its simulation result.

 

(Simulation Result  --> OK!!!)

              ________

VD       _|               |______

              ______

HD       _|           |________

            ___          _______

HBLK1       |_____|

            ___          _______

HBLK2       |_____|

             _   ______   _   _

H1      _|  |_|           |_|  |_|  |_

          _   _             _   _    _

H2       |_|  |______|  |_|  |_|

 

(Device ADDI7013 Output --> HBLK1, HBLK2 effects is ???)

              ______          _____

VD       _|           |_____|

              ______          _____

HD       _|           |_____|

             _   _    _    _    _   _

H1      _|  |_|  |_|  |_|   |_|  |_|  |_

          _    _   _    _    _    _   _  

H2        |_|  |_|  |_|  |_|   |_|  |_| 

 

 

(afestartup.lf)

C022      0001       // software reset

C031      0001       // SCK_SELECT

C020      004F       // Enable AFE and REF

C021      0000       // CLI DIVIDE

C086      008b      // REQUIRED STARTUP WRITE

C087      0000       // REQUIRED STARTUP WRITE

C0A0      1000       // REQUIRED STARTUP WRITE

C0C0      0001       // REQUIRED STARTUP WRITE

C0C1      0048       // REQUIRED STARTUP WRITE

C020      005F       // Enable Timing core

C030      0001       // CLI SELECT wait at least 200 us after TG enable

C001      0002       // CDS Gain

C002      000F       // VGA Gain Channel 1

C003      000F       // VGA Gain Channel 2

C006      01EC      // CLAMPLEVEL A

C007      01EC      // CLAMPLEVEL B

C041      1800       // H1POSLOC,H1NEGLOC --> H1A OK

C042      1800       // H2POSLOC,H2NEGLOC --> H1B OK

C043      0018       // H3POSLOC,H3NEGLOC --> H2A OK

C044      0018       // H4POSLOC,H4NEGLOC --> H2B OK

C045      2000       // HL1POSLOC,HL1NEGLOC

C046      2000       // HL2POSLOC,HL2NEGLOC

C047      0006       // RG1POSLOC,RG1NEGLOC  --> RESET

C048      0006       // RG2POSLOC,RG2NEGLOC

C049      2000       // SHDLOC_A,SHPLOC_A

C04B      2000       // DOUTPHASEP,DOUTPHASEN

C04D      0000       // HBLKRETIME,HBLKPOL --> 0x5555 (?)

C04E      0000       // FINERETIME

C000      0241       // ENABLE BLACK CLAMP, SAMPLING MODE

C0CF      0003       // REQUIRED STARTUP WRITE

C027      0001       // MASTER MODE

7C0B      000F       // ISATGSTANDBY

7C0F      0002       // ISATG STARTUP write

7C80      0000

7C81      0000

7C82      000A

7C83      0000

7C88      0000

7C89      0000

7C8A      000A

7C8B      0000

7C74      0004       // ATIMER_SEL1

7C75      0000       // ATIMER_SEL2

7C60      FFFF

7C61      FFFF

7C64      FFFF

7C65      FFFF

7C70      FFFF

7C71      FFFF

7C72      FFFF

7C6C      0033

7C6D      0000

7C6E      0000

7C62      9C3F

7C63      0000

7C66      0F9F

7C67      0000

7C69      FFFF

7C6B      FFFF

7C68      FFFF

7C6A      FFFF

7C51      0000       // OUTSTANDBY1 STIMER[31:16]

7C52      AAFF     // OUTSTANDBY2 STIMER[47:32]

7C53      00FF       // OUTSTANDBY3 STIMER[63:48](Only Required for Simulation)

7C54      0000       // OUTSTANDBY4 ATIMER[15:0]

7C55      0000       // OUTSTANDBY5 ATIMER[31:16]

7C56      0000       // OUTSTANDBY6 ATIMER[47:32]

7C41      0000       // OUTREG1

7C42      AAFF     // OUTREG2

7C43      00FF       // OUTREG3(Only Required for Simulation)

7C44      0000       // OUTREG4

7C45      0000       // OUTREG5

7C46      0000       // OUTREG6

7C49      C000      // OUTEN1

7C4A      FFFF       // OUTEN2

7C4B      03FF       // OUTEN3(Only Required for Simulation)

7C4C      FFFF       // OUTEN4

7C4D      FFFF       // OUTEN5

7C4E      FFFF       // OUTEN6

C023      0000       // DISABLE VD/HD AS INPUTS

C024      0002       // ENABLE VD/HD AS OUTPUTS

C026      0001       // CONFIGURE SYNC PIN AS SYNC

C028      0000       // SYNCPOL/VDHDPOL/MSHUTPOL/VSUBPOL=0  --> 0x0000 (rising edge trigger)

C080      0000       // ENABLE LVDS OUTPUTS

C082      0071       // TCLK_DEL, DUAL PORT MODE --> 0x0071

C083      0060       // ENABLE CLIP_ZS, CLIP_FS, [1:0]=REQUIRED WRITE

C088      0006       // OUTPUT 6 SYNCWORDS, 0 CTRLWORDS

C089      0000       // SYNCWORD0

C08A      0000       // SYNCWORD1

C08B      FFFF       // SYNCWORD2

C08C      FFFF       // SYNCWORD3

C08D      0000       // SYNCWORD4

C08E      0000       // SYNCWORD5

C097      0003       // CWB0=HD

C099      0001       // RISING EDGE TRIGGER ON CWB0

C025      00FF       // ONLY FOR SIMULATION (not required for actual device) --> 0x0000 (?)

C02F      0050       // SDATA out for register read-back mode

 

 

(tgstartup.lf)

C024      00FE       // ENABLE DATA, GPO

C058      4444       // H1 Driver Strength

C059      4444       // H2 Driver Strength

C05A      4444       // H3 Driver Strength

C05B      4444       // H4 Driver Strength

C05C      4444       // HL1 Driver Strength

C05D      4444       // HL2 Driver Strength

C05E      4444       // RG1 Driver Strength

C05F      4444       // RG2 Driver Strength

4000       0000                       // Set Mode 0

7c34       0018                       // ISR jump to 24

7c22       0000       // ILAT (CLEAR INTERRUPTS)

7c20       FFEF       // enable interupts

7c22       0010       // ILAT to trigger VD ISR

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