1. DIGITAL AUDIO
We have no plans to use the digital audio with the ADV7535 MIPI-HDMI bridge chip.
In that regard the data sheet indicates if audio is NOT used to tie LRCLK (pin D3) and SCLK/MCLK (pin C2) to ground. Will do, but should I also tie SPDIF/I2S to ground?
Fyi: I see that I can also disable I2S or SPDIF via i2c control registers by setting the I2S_ENABLE bit (0x0C) to ‘0’ and disable SPDIF by setting SPDIF_EN bit (0x0B) to ‘0’, respectively?
2. POWER SUPPLY SEQUENCING
I find no information in the ADV753x data sheets that addresses any power sequencing requirements for the 3v3 and 1v8 supplies used by the ADV7535.
In our proposed ADV7535 design the 3v3 comes up first and is the source for the 1v8 regulator, so the latter will slightly lag the 3v3 supply (I estimate ~0.5 msec).
In your reference design (Analog Devices EVAL-ADV753XEBZ), the input 7v5 supply simultaneously supplies 3v3, 5v0 and 1v8 regulators – all using ADP3333ARM1 LDOs.
So for the ADV7535, all the supplies come up essentially simultaneously.
However, the ADV7533 can operate with either 1v2 or 1v8 to pins D4 and E3. In the reference design, the ADV7533 uses the 1v2 supply, which is sourced by the 5v0 supply so it will lag 3v3 and 1v8 slightly. It would thus seem that neither probably has any power sequencing requirements.
Can you confirm that neither device (the ADV7533 or ADV7535) have an power sequencing restrictions?