We use AD9548 EVAL board to test our Crystal. Compare the 1pps PLL output with our 1pps Reference to evaluate our Crystal's stability.
- 20MHz CMOS TCXO for SYSCLK
- SYSCLK 1000MHz
- 1PPS on Reference B
First we can see the frequency locked, minutes later, the frequency unlocked. We check the DPLL is active , there are five status: switching.phase lock,frequency lock,hitless,slew rate limited, Only Frequency Lock and Hitless is OK.
So would you help to check my profile attached?
In addition, we will have many crystals with different frequency, with different crystal , how could i configure the parameters?