We are evaluating the AD9739A DAC and we had a couple of questions regarding DCI_DEL parameter:
1. What does the 10 bit code correspond to in delay steps (ps or ns) ? Is there a one-to-one map ?
2. Is the delay from DCI_DEL imparted to the DCI signal alone, wrt the data bus ? Or both the DCI signal and data bus get delayed equally ? I wanted to confirm if FPGA based DCI delay adjust is necessary or not
Thanks in advance !