Our client is evaluating our RF boards which use HMC833 PLL. This PLL generates LO from 1.2 to 1.6GHz range in 10MHz steps. RF signal is from 1.1 to 1.5GHz, so we work with 100MHz IF signal. They see PLL locking issues at a bunch of discrete frequencies within 1.2 to 1.6GHz. They are 1380, 1400, 1410, 1450, 1470, 1480, and 1490 MHz. I have provided a couple of examples in the attachment. One at 1350MHz (good LO) and other at 1380MHz (bad LO, Lock failure). I have also attached our register set. Only one register changes between the two. But results are different.
Any feedback is greatly appreciated. We suspect some of the register settings may be wrong in this frequency range.