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AD9361 initial failure when enable the internal FIR filter with x4 interpolation

Question asked by wanglixin on Feb 1, 2016
Latest reply on Feb 1, 2016 by wanglixin

Hi,

     We use Microblaze NO-OS AD9361 software running on KC705 Xilinx platform. It can work well with the original initial parameters.

But if I enable the FIR with x4 interpolation,it comes up the error message"Failed-at least one of the clock rates must be equal to the DAC_CLK(lvds) rate".

     And I find it reported from the function ad9361_validate_trx_clock_chain.In this function,it compare the DATA_CLK which should be equal to the 2*SAMPLE CLOCK (in 1r1t mode ) with the rx_clock_path[i],if there is no clock be equal to the DATA_CLK,then return

-ENIVAL error symbal.

I enable the FIR filter as follow steps:

         set_tx_fir_coff();

         set_rx_fir_coff();

         set_tx_sampling_clock(40000000);//40Mhz

          enable_trx_fir_filter(1)

    

     and tx fir configured as x4 int, 128 taps, 0 gain;

           rx fir configured as x4 dec,128 taps,-6 gain.

 

and it will recalculate the clock chain,then I get

     rx_clock_path:{1280000000,640000000,320000000,160000000,160000000,40000000};

     tx_clock_path:{1280000000,320000000,320000000,160000000,160000000,40000000};

the the drive will call the ad9361_validate_trx_clock_chain function,then the wrong message show up.but it exeute rightly,cause there is no 80000000 (lvds DATA_CLK rate) on the rx_clock_path chain.


     Is there somewhere I ignored? and how should I configure my ad9361 to make it work well?Thanks!

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