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AD9361 initial failure when enable the FIR filter with x4 interpolation

Question asked by wanglixin on Feb 1, 2016
Latest reply on Feb 1, 2016 by wanglixin

Hi,

We use MicroBlaze NO-OS software on KC705 Xilinx platform.It can work well with original initial parameters.

But when we enbale internal FIR filter with x4 interpolation,the uart console report error message:" Failed - at least one of the clock ratesmust be equal to the DATA_CLK (lvds) rate".

My platform inital configuration is as follow:

rx1tx1 mode ,

lvds digital interface,

inital clock chain :

        rx_clock_path{ 1280000000,320000000,160000000,80000000,40000000,40000000},

        tx_clock_path{ 1280000000,160000000,160000000,80000000,40000000,40000000},

tx fir filter: x4 int  128taps 0gain

rx fir filter: x4 dec 128taps -12gain

 

enable fir filter with follow steps:

     set_tx_fir_coff();

     set_rx_fir_coff();

     enable_trx_fir();

 

After I enable trx fir filter simultaneously,the API will recalculate the clock chain,then we get

        rx_clock_path{ 1280000000,640000000,320000000,160000000,160000000,40000000},

        tx_clock_path{ 1280000000,320000000,160000000,160000000,160000000,40000000},

 

And it will call the funtion "ad9361_validate_trx_clock_chain",and the error message will show up. I am wondering if the function has a bug?

because when I enable the fir filter with x4 interpolation the follow function will return -EINVAL rightly.

static int32_t ad9361_validate_trx_clock_chain(struct ad9361_rf_phy *phy,

  uint32_t *rx_path_clks)

{

  int32_t i;

  uint32_t data_clk;

  data_clk = (phy->pdata->rx2tx2 ? 4 : 2) * rx_path_clks[RX_SAMPL_FREQ];

  for (i = ADC_FREQ; i < RX_SAMPL_CLK; i++) {

  printf("ad9361_validate_trx_clock_chain:  %"PRIu32";  %"PRIu32" \n\r",rx_path_clks[i], data_clk);

  if (abs(rx_path_clks[i] - data_clk) < 4)

  return 0;

  }

  dev_err(&phy->spi->dev, "%s: Failed - at least one of the clock rates"

  "must be equal to the DATA_CLK (lvds) rate", __func__);

  return -EINVAL;

}

 

the dac_clk will be 2 mutiple with the tx sample clock (40000000),so we get the 80000000Hz as the digital dac_clk.

but the function above is only allowing that at least one of the clock rates must be equal to the DATA_CLK (lvds) rate. so it will be initial failure.

 

in summary:

     My question is whether the issue I descripte above is a bug?

     and if not,How should I configure my ad9361 to make the internal fir filter function well?

     can I commented out the ad9361_validate_trx_clock_chain function when I enable the trx clock chain to make it work?

 

     looking forword to hear your reply!

                                                                                                                                                                     Thank you!

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