I am building a PLL around an ADF4002. AVdd/DVdd is 3.2V and Vp is 5V. My loop filter is a shunt 150n capacitor in parallel with a series 680n and 2k7 resistor; it connects to the cathodes of a back to back pair of varicap diodes of my VCO via a 47k resistor. All is well when generating the lower frequencies; the loop locks nicely to a stable frequency. However, the tuning voltage refuses to rise above about 2.3V. So if I try to generate higher frequencies the loop fails to lock and the frequency does not reach the higher value, and I can see the less significant digits churning on my counter timer.
I have checked the pin connections and the voltages around the ADF4002 but I cannot find any mistakes. A second similar synthesizer I built also produces the same symptoms. Is it possible that I have blown the CP output of the chips? Or can anyone offer suggestions as to what could be wrong?