AnsweredAssumed Answered

how to adjust FMCOMMS1 ADC sampling rate at 40 MHz and multiples ?

Question asked by LouisBe on Jan 28, 2016
Latest reply on Mar 2, 2016 by charlyelkhoury



I am using the FMCOMMS1 card and reference designs. I am trying to set-up ADC and DAC operations at (standard) multiples of 40 MHz. Is someone in the community and/or in other posts have been able to do so ?


I tried setting by software the different values (using the cfg files), but I always have a multiple of the 122.88 MHz VCXO freq.


Also, I am a bit confused by reading the 'AD-FMCOMMS1-EBZ Functional Overview' (Rev 15 jul 2015) : it indicates that there is a configurable 30 MHz clock coming from the FPGA which 'feeds a 30 MHz clock to the AD9523'. From measurements I took on output 1 of AD9548, it measures 122.88 MHz. The output 0 (which should be 122.88 / 4 = 32.72 MHz) of the AD9548 clock is on Ref B of AD9523, and is used by default in the ref design. So, is it 30 MHz or 30,72 MHz ?


If so, do I have to change the tuning words of the AD9548 to obtain the 30 MHz (which would provide multiples of 40 MHz in the rest of the chain) ?


Note I am using for this request the older FMCOMMS1 HDL ref .design (with XPS).  I will be looking at the newer Vivado ref. design to see if a 40 MHz sample rate can be programmed.


Thanks for the feedback,