I am trying to integrate AD9250 (eval board) with VC707 evaluation board. I have written my own SPI VHDL code with the following commands.
I am first writing the following registers with the corresponding word and finally trying to read back from 1 register.
- write 0x00 with 3C
- write 0x80 with 0F
- write 0x5F with 15
- write 0x09 with 01
- write 0x82 with 02
- write 0x83 with 31
- write 0x6E with 81
- write 0x70 with 1F
- write 0x5E with 22
- write 0x5F with 14
- write 0x80 with 09
- write 0x3A with 10
- read 0x01 (output of all 1's)
However, when I implement the above SPI commands using VHDL, I am seeing the following in oscilloscope.
The SDI, SCLK,CS signals are perfectly fine from FPGA all the way till the interpozer card (probed at TP614, TP615, TP610 on the eval board). But when the signals are buffered though U601 IC (NC7WZ07P6X) on eval board to AD9250 IC, the DUT_SDIO signals gets messed up, but DUT_CSB and DUT_SCLK are perfectly fine.
Also, even for write commands, I am getting back signals from AD9250_EBZ through SDI.
I have attached the signal waveform form the oscilloscope with this post.
Can you let me know where I am going wrong and how to resolve this ?