I have few question about ADV7181D.
I read the ADV7181D's datasheet.
This means to use ADV7181D's ADC we must input the signal 1.86V - 0.8V ~ 1.86V ~ 1.86V + 0.8
And the dynamic range is 1.6V , so if the signal is bigger than 1.6V , it will be clipped of ADC range.
Is my understanding is correct?
And does this device has some resister to adjust the speed of the analog clamp operation?
And if we use the Max value for that , is there the concern matter?
To sync the analog input signal(CVBS) , the spec says sync depth is 60mVmin ~ 600mVmax.
I can understand that sync depth is 60mV~600mV but does ADV7180 can detect sync signal when the input is lower than GND?
=> Does ADV7180 can synchronize if the sync depth is larger than 60mV which in case the sync signal lowest voltage is under GND?
Or do we have to secure more than 60mV from ADC Min 1.06V?
I want to know that because it look like to sync the CVBS signal , the only spec is sync depth.
I wonder that before starting clamp , AIN pin signal is almost 0V so the sync signal is lower than GND.
With my understanding , the device will start clamp and when the sync depth is larger than 60mV from GND or ADC min voltage,
the device will start synchronizing and it would take maybe few hundreds m.sec.
Is this correct?
Can you give me some advice about this?