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AD9852 Project

Question asked by Alejandro17 on Jan 27, 2016
Latest reply on Feb 22, 2016 by JLKeip

Greetings

I am currently developing an academical and research project at UNIVERSIDAD CENTRAL DE VENEZUELA (Central University of Venezuela) involving one of your integrates, more specifically an AD9852 DDS as a BPSK modulator for a amateur radio band, therefore I have a couple of questions that I would really appreciate to be help with.

1) What values of jitter and rise edge for the reference external clock are recommended for minimum noise in the output (or noise figure for what it matters)

2) Just to be sure, is it entirely necessary for the data input (i.e. a serial stream via SPI interface) to be an even sub multiple of the reference clock (in this case, the reference clock obtained by multiplying the external clock) for the modulation to be accurate?

I’m also aware of the update clock function of the integrate, so for example, let’s say my system clock runs at 250MHz, my SPI data input goes at 10Mbps, and I do an external, interruption driven clock update for every byte send via SPI. Would this process be OK for a correct BPSK modulation, so I don’t lose any information by wrong sampling processes on the integrate?

3) In the evaluation board available for the AD9852 one can see that the anti aliasing filter used is a chebyshev-cauer. I’m aware that a flat response on the pass band is highly desirable, but this filter also has an overshoot higher than 10%. Would you consider a filter with this model to be desirable for modulation applications? In this case a BPSK modulator.

4) Finally, in the Analog Dialogue, Volume 46, Number 1, 2012 issue, the process for a zero crossing switching BPSK/FSK is discussed. It is easy to understand the concept of using dual channels and the Grand Repetition Rate (GRR) between Mark and Space to force the system to switch at zero crossing, but is far not clear how can one easily implement it with the available integrates. Since I’m using an AD9852 which have an additional control DAC I’m really interested in the actual process of implementing the zero crossing switching.

I would really appreciate any information about this issues that could be provided

Thanks in advance

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