I would like to pull an analog RF input signal from the AD9361 core to be used for in an algorithm. We are using the ADFMCOMMS3 SDR connected to a Zynq-zc702 board.
I've found the data being transferred via a 64-bit bus to the AXI through the DMA, is this evenly split into the two receiving signals (each signal owning 32-bits respectively)? Is this the best place to pull the signal data from? How should this data be read?
Additionally, I came across a note saying:
"ZC702 – supports 2 x Ethernet FMCs, but there’s only enough FPGA resources to configure the 8 MACs with FIFOs (not DMAs)." How does this affect the way we will need to route our signals?