I want to simulate a loop filter for the AD9520-5 using an external VCO in ADIsimCLK.
For the AD9520-5 there is only a configuration option for clock distribution with disabled PLL (no loop filter, no external VCO).
Can I instead select another AD9520-x and make a simulation with disabled internal VCO? Does all AD9520-x share the same loop dynamics?
Furthermore I am unsure if I have chosen the right PLL-Eval-Board for my project in generell.
Goal is to phase-lock an 80 MHz 'slave'-VCO to a 240 MHz reference-source. With the lowest Jitter as possible. Time to lock is not important.
Input signals to the PFD are 3.3V LVPECL.
Beside the AD9520-5 I took a look at the HMC984LP4E.
It would be great, if you have any advice for me.