I have an initial custom design with the AD9361 and an Artix-7 using Vivado 2014.2. Now, I want to add LPDDR2 memory, so I generated a standalone LPDDR2 core and created an AXI wrapper. The MIG with LPDDR2 only give you one output clock, the ui_clk, for the other IP cores, but I also need a 200 MHz clock so I connected ui_clk to a clock wizard. After doing this, I got some rx_clk and 100 MHz clock wizard output timing errors. Are there any reference designs with LPDDR2 memory? Are there any recommended ways to further constrain rx_clk or the 100 MHz input clocks to the AD9361 core? What are the max delays of these clocks?