I have a question about ADF4351.
If the write sequence is stopped before receive 32 clock and then the LE is moved to high, is the broken data thrown away from shift register ?
Or the write sequence is aborted ?
If the broken data are not thrown away, and If the LSB 3bits of the broken data are "000", I think the internal registers may be updated by the broken data.
Can ADF4351 prevent this improper operation ?