I need to use AD9364 with external reference clock. To lock to an external reference and generate a clean reference clock (40MHz) for AD9364 I use the AD9547. The AD9364 reference clock input accept a level of 1.3Vpp but the AD9547 can output signal in differential CMOSLVDS or VLPECL.I want to use both differential output (positive and negative) to lock two different AD9364. The second ouput of the AD9547 generate a different frequency clock used for another purpose.
Can you suggest the proper interface/adaptation network to accomplish the AD9361 level and phase noise requirements.