In AD9364 receiver chain, How do the I and Q data get multiplexed and How do the ADC clock rate and decimation filters affect the multiplexing? How could you demultiplex the data?
The information is contained in the documentation available at this link:
AD9361 and AD9364 Integrated RF Agile Transceiver Design Resources | Design Center | Analog Devices
The output data format depends on the configuration of the chip.
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