Our customer have some questions when they development project now:
They have two source: One is digital I2S input from SoC, and another is AUX input converted by audio ADC; and it have the possible that the two source will into ADAU1451 at the same time.
According to digital I2S input signal native sample rate, SoC change frequency on BCLK/LRCK/MCLK output. The rule is
* Normal SoC steaming: 12.288MHz MCLK: for any sample rate
for sampling rate 44.1 kHz and multiples: select 22.5792 MHz MCLK
for sampling rate 48 kHz and multiples: select 24.576 MHz MCLK:
ADAU1451 should be able to get various sample rate as input, and output the same sample rate to amplifier.
Do you have any comment for this design, any risk for our customer should notice?
And they have some questions:
- 1.Could share the example flow to use ASRC feature? If no example flow on ADAU1451, the flow on similar DSP is also OK.
- 2.When input sample rate is changed, MCU will change setting on ASRC input and MCLK out. Our customer expect sample rate on all I2S ports will based on “MCLK out” to change, is it correct? For example, when change MCLK out from x512 to x256, sample is changed from 48KHz to 96KHz.
- 3.Do they need to mute DSP during sample rate change period?