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AD-FMCDAQ2-EBZ HDL Reference Design

Question asked by SDR on Jan 24, 2016
Latest reply on Jan 26, 2016 by rejeesh

The Block diagram of the AD-FMCDAQ2-EBZ HDL Reference Design shows 64 bits@ 250 Mhz at each of the Channel processing outputs. What would be the output if we enable the DDC and halfband filtering in 9680. Also what would be the IQ format at the output.

Thanks in advance.

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