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ADV7842 TMDS PLL Sometimes Not Locking

Question asked by DRC on Jun 22, 2011
Latest reply on Jun 27, 2011 by GuenterL



I'm reading back the following registers:

TMDS_PLL_LOCKED ([HDMIMap][0x04][1])

TMDSPLL_LCK_A_RAW ([IOMap][0x6A][5])

TMDS_CLK_A_RAW ([IOMap][0x6A][1])


I used the script posted in the following:


At first, everything is fine and all 3 status registers are set to 1.


When I unplug and replug my cable (without making any configuration changes), often the two PLL-Lock status bits are set to 0 and are stuck like that.  TMDS_CLK_A_RAW (the bit that tells you if a clock is detected) is always 1 when the cable is plugged in.


So it appears sometimes the TMDS PLL is not locking.  If I reset the ADV7842 and reconfigure it using the script, everything is fine.


I also noticed that if I probe the clock signal on my board with my scope (using an active probe), the PLL locks immediately and the two status bits are now 1.  Hopefully that's a clue.


Is there something I'm missing here?  Do I need to reset the PLL somehow?


Let me know if you need any more info or measurements.