I have a Danville Signal ADSP21469+ICE kit which I understand is similar to the EZ-Lite kit for many configuration features.
I have a functioning design which is a 5 way active crossover using the FIR accelerators for the crossover, core and IIR accelerators for parametric EQ.
However, to implement delay lines to correctly align the output data channels I have run out of memory. I'm currently using about 25K words of RAM but need an additional 42k words for delay lines.
I cannot seem to get the DDR memory to work either - maybe my lack of understanding or maybe a fault with my Danville board.
I may have to continue to try to get the DDR working as a last resort however, I'd rather use the internal RAM as there is enough to do what I need if it can be accessed / reconfigured.
The LDF file shows shows Blocks 0-3 with 1.5, 1.5, 1 & 1 MBit memory allocation - why it's configured this way seem very ineficient. The configuration also seems to be very complicated and I'm struggling to understand it.
There has to be a way to reconfigure this to maximise the internal RAM. I only have about 25k words of program data but need about 67K of data RAM. It seems crazy the standard configuration is so limited in memory. 5Mbit = > 150k Words so 67-70k or even 80k word in the DM memory sould be possible without a problem.
It's also frustratingly misleading from the documentation when you look at the ADSP2146 - 5Mbits = a ****-load of memory but bugger all of it is actually available to use as DM memory. It's not until you start using this DSP you begin to find all the limitations...
Is there a simple tutorial or setup document to show how to reconfigure the RAM to maximise the DM RAM?
It's incredibly frustration to have my design almost complete only to come potentially unstuck right at the end due to a memory issue that's not actually documented well up-front.