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ad1939 ADC slots data format

Question asked by Shamsul on Jan 20, 2016
Latest reply on Jan 26, 2016 by Shamsul

Hello,

 

I am using blackfin BF532 to interface ad1939. I have configured the codec by spi and it outputs the adc data via the sport interface to the blackfin through interrupt. This interrupt service routine is executed after a complete frame of input data has been received from the sport interface. Mine is 48kHz sampling rate, I am using PLL to clock out ADC data, source of PLL is 12.288Mhz clock feeded into MCLK pin of CODEC. Also I am using TDM Aux mode in my ADC channels

 

Now from AD1939 datasheet I know full scale differential input is 1.9Vrms. So I am trying to do very simple thing here just to get things started.

 

On my input pins of ADC channel 1, (ADC_L1  slot1 of TDM data streem) (pin 53, pin 54)

I am putting on 2.5V DC and 0.65V DC respectively to get full scale digital output in my TDM slot 1

Then putting on 1.5V DC and 1.5V DC respectively to get 0 digital output in my TDM slot

 

If I look into Visual DSP++ debugger expression window I see it gives 2s compliment value which are ok.

 

Now If I put this same dc voltage (2.5/0.65 & 1.5V/1.5V DC) on ADC channel 2 (which should be ADC_R1 SLOT2 in TDM stream ) I see that 2s compliment value is not consistent all the time. I put a break point in my ISR routine and I see that correct 2s compliment value do not show up all the time  & it gives some garbage value in between for ADC 2 channel. However I don’t see this problem on ADC channel 1

 

What might be the reason for ADC channel 2 not to give consistent 2s compliment value?

 

Also just to be sure that I am doing right, I am taking that 2s compliment value converting to decimal then using this equation to get actual voltage

 

(decimal value x 1.9V)/(2^23 -1)

 

Please let me know if this calculation is right or not.

 

Following is my register setting for CODEC 1939 and blackfin SPORT configuration

 

  {  PLL_CONTROL_0      , 0x98 } , //80

  {  PLL_CONTROL_1      , 0x08 } ,//00

  {  DAC_CONTROL_0      , 0x80 } , // 1 bit delay

  {  DAC_CONTROL_1      , 0x74 } , //74

  {  DAC_CONTROL_2      , 0x00 } , // no confusion

  {  DAC_Channel        ,      0x00 } , // no confusion

  {  DAC_VOLUME_1       , 0xFF } ,

  {  DAC_VOLUME_1       , 0xFF } ,

  {  DAC_VOLUME_2       , 0xFF } ,

  {  DAC_VOLUME_3       , 0xFF } ,

  {  DAC_VOLUME_4       , 0xFF } ,

  {  DAC_VOLUME_5       , 0xFF } ,

  {  DAC_VOLUME_6       , 0xFF } ,

  {  DAC_VOLUME_7       , 0xFF } ,

  {  ADC_CONTROL_1      , 0x00 } , // no confusion

  {  ADC_CONTROL_2      , 0x40 } ,

  {  ADC_CONTROL_3      , 0xe8 } // d8

 

#define INTERNAL_ADC_L0                                        0

#define INTERNAL_ADC_R0                                        1

#define INTERNAL_ADC_L1                                        2

#define INTERNAL_ADC_R1                                        3

#define INTERNAL_DAC_L0                                        0

#define INTERNAL_DAC_R0                                        1

#define INTERNAL_DAC_L1                                        2

#define INTERNAL_DAC_R1                                        3

#define INTERNAL_DAC_L2                                        4

#define INTERNAL_DAC_R2                                        5

 

void Init_Sport0(void)

{

                // Sport0 receive configuration

                // External CLK, External Frame sync, MSB first

                // 32-bit data

                *pSPORT0_RCR1 = RFSR;

                *pSPORT0_RCR2 = SLEN_32;

               

                // Sport0 transmit configuration

                // External CLK, External Frame sync, MSB first

                // 24-bit data

                *pSPORT0_TCR1 = TFSR;

                *pSPORT0_TCR2 = SLEN_32;

               

                // Enable MCM 8 transmit & receive channels

                *pSPORT0_MTCS0 = 0x000000FF;

                *pSPORT0_MRCS0 = 0x000000FF;

               

                // Set MCM configuration register and enable MCM mode

                *pSPORT0_MCMC1 = 0x0000;

                *pSPORT0_MCMC2 = 0x101c;

}

 

void Init_DMA(void)

{

                // Set up DMA1 to receive

                // Map DMA1 to Sport0 RX

                *pDMA1_PERIPHERAL_MAP = 0x1000;

               

                // Configure DMA1

                // 32-bit transfers, Interrupt on completion, Autobuffer mode

                *pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;

                // Start address of data buffer

                *pDMA1_START_ADDR = (void *)iRxBuffer1;

                // DMA inner loop count

                *pDMA1_X_COUNT = 8;

                // Inner loop address increment

                *pDMA1_X_MODIFY     = 4;

               

               

                // Set up DMA2 to transmit

                // Map DMA2 to Sport0 TX

                *pDMA2_PERIPHERAL_MAP = 0x2000;

               

                // Configure DMA2

                // 32-bit transfers, Autobuffer mode

                *pDMA2_CONFIG = WDSIZE_32 | FLOW_1;

                // Start address of data buffer

                *pDMA2_START_ADDR = (void *)iTxBuffer1;

                // DMA inner loop count

                *pDMA2_X_COUNT = 8;

                // Inner loop address increment

                *pDMA2_X_MODIFY     = 4;

}

 

void Enable_DMA_Sport0(void)

{

                // enable DMAs

                *pDMA2_CONFIG           = (*pDMA2_CONFIG | DMAEN);

                *pDMA1_CONFIG           = (*pDMA1_CONFIG | DMAEN);

               

                // enable Sport0 TX and RX

                *pSPORT0_TCR1 = (*pSPORT0_TCR1 | TSPEN);

                *pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN);

}

 

EX_INTERRUPT_HANDLER(Sport0_RX_ISR)

{

                // confirm interrupt handling

                *pDMA1_IRQ_STATUS = 0x0001;

 

                // copy input data from dma input buffer into variables

                iChannel0LeftIn = iRxBuffer1[INTERNAL_ADC_L0];

                iChannel0RightIn = iRxBuffer1[INTERNAL_ADC_R0];

                iChannel1LeftIn = iRxBuffer1[INTERNAL_ADC_L1];

                iChannel1RightIn = iRxBuffer1[INTERNAL_ADC_R1];

               

               

                D = ((iChannel0LeftIn)*1.9)/(2^23 - 1); // iChannel0LeftIn is converted from 2s compliment to decimal

 

}

So I am putting break point just after D value and seeing those 2st compliment value over this local register (iChannel0LeftIn, iChannel0RightIn )

 

So for channel one iChannel0LeftIn gives proper 2s compliment value which does not change. however iChannel0RightIn does not give consistent 2s compliment value, shows some garbage value on VisualDSP++ debugger.

 

Thanks for your time!

 

Shamsul Siddiqui

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