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can not understand axi_ad9361_dev_if.v of axi_ad9361 IP

Question asked by jlqsczw_2007 on Jan 20, 2016
Latest reply on Jan 21, 2016 by CsomI

Hello, everybody.

I readed the code of axi_ad9361_dev_if.v  in reference design of ADI and found that I can not understand it.

For example,

 

  // receive data path interface

  assign rx_align_s = rx_frame_n_s ^ rx_frame_p_s;         ------------ why ?

 

  always @(posedge l_clk) begin
    rx_data_p <= rx_data_p_s;           -------------what's the meaning of _s ?
    rx_frame_p <= rx_frame_p_s;
    rx_ccnt <= rx_ccnt + 1'b1;
    if (rx_ccnt == 2'd0) begin
      rx_calign <= rx_align;           --------rx_calign, rx_align,rx_align_s, what does the code wanna do ?
      rx_align <= rx_align_s;
    end else begin
      rx_calign <= rx_calign;
      rx_align <= rx_align | rx_align_s; ------------???
    end
  end

 

 

 

 

  // receive data path for single rf, frame is expected to qualify i/q msb only

  always @(posedge l_clk) begin
    rx_error_r1 <= ((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;--------why 1100 and 0011??
    rx_valid_r1 <= (rx_frame_s == 4'b1100) ? 1'b1 : 1'b0;-----------???
    if (rx_frame_s == 4'b1100) begin
      rx_data_r1[11: 0] <= {rx_data_d[11:6], rx_data[11:6]};------why?
      rx_data_r1[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
    end
  end

 

......

...... and so on.

 

This verilog file has few comments.

There are too many things that I can not understand in the code.

I can not find the solution in ad9361 datasheet either.

Is there anything  useful that can help me to understand the code???

Thanks.

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