in a current design I use ADAU1451.
Some of the serial ports are supposed to work in a slave mode (some I2S, some TDM16).
According to the Sigma Studio in a slave mode I need to assign BCLK and LRCLK for the slave IN and OUT ports to one of the 4 clock domains 0 to 3.
I couldn't find where these clock domains are configured and how.
I see clock generators setup, but can't figure out if these are related to the above serial ports clock domains and how.
Will appreciate any clarification of this issue.