I am trying to read data from the AD7609 using the Eval-AD7609 board and an FPGA. I have made a number of modifications to the board to use it without the "CED Board Connector".
1) SL9 and SL10 --> VDRIVE and AVCC on board connectors (5V each)
2) SL7 & 8 --> bring the data out to on-board SMB pads
3) R3/R4 --> Serial mode
I am trying to read the data during conversion but never see that the BUSY pin falls low. I also never see the FRSTDATA pin go high.
My timing sequence is as follows (verified using a scope):
1) RESET high for 2.5 microseconds
2) RESET low for ~2.5 microseconds (us)
3) CONVST A & B Low for 50 nanoseconds (ns) (check if BUSY is high before continuing to CS low)
4) CS low & wait for FRSTDATA to go high <------FAIL (FRSTDATA never goes high)
5) Timeout and go back to RESET (step 1)
If I trick my FPGA into thinking FRSTDATA went high,
I read out 0x00000 on all channels of DATA A (1-4) and 0x3FFFF on all channels of DATA B but BUSY never falls
Is there some behavior of the chip that is not specified to start it up correctly? For example, am I supposed to allow it to convert on the first read without trying to read the (non-valid) data at Step 4 (from above)?
Any help is appreciated.