thank you for your reply. I used the IIO devices to configurate the ARRADIO (AD9361) and it works fine.
Now, I have to write/read the I and Q data inside the FPGA. The I/Q data are then used by other FPGA components. In ADI Reference Designs HDL User Guide [Analog Devices Wiki] you propose to use a FIFO as an interface to the DAC and ADC cores to read and write the I/Q data with own logic in the FPGA domain. Shall the FIFOs connect to the "system_top|system_bd:i_system_bd|util_adc_pack:adc_pack" and "|system_top|system_bd:i_system_bd|util_dac_unpack:util_dac_unpack" components ? or how I can write/read the I/Q data to/from the AD9361 from the FPGA?