AnsweredAssumed Answered

ad9361 tx and rx error, please help me.

Question asked by dwtguh on Jan 19, 2016
Latest reply on Jan 20, 2016 by dwtguh

i am make a custom ad9361 board. fpga to ad9361 is lvds, and i use 3F5 to loop test, Digtal interface is ok.but when i send a tone, the result is like the picture blow:

QQ图片20160119182944.jpg

the tx signal is LO-CLK/8, LO=800MHz, CLK=30.72MHz

 

    /* Rate & BW Control */

    {983040000, 245760000, 122880000, 61440000, 30720000, 30720000}, //uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

    {983040000, 122880000, 122880000, 61440000, 30720000, 30720000}, //uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

 

FPGA for ad9361 is use axi_ad9361_dev_if. arm code is use no-os code. Both is download from adi.

 

QQ图片20160119184140.png

 

i dont know how debug it anymore, please help me. thanks!

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