I am using the FMCOMMS1 reference design and would like to write to the DAC with my own desired values.
I must have a data generator written in hdl, . In that case i have disconnect the dma from the core, and connect my generator to it.
I chose DDS ip as generator. i add my DDS ip and connected it to the dac ( in the fmcomms1 block diagram in vivado)
I've also defined DDS input and output ports into the system_top. But when I synthesis program, I get the error encountered. Can you help me?