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ADF41020 Setting using ADI Int-N PLL S/W

Question asked by Thomas2016 on Jan 17, 2016
Latest reply on Feb 5, 2016 by Brigid.Duggan

Hello, I am trying to set ADF41020 PLL chip at 17.08032GH using ADI Int-N PLL S/W.

I read the ADF41020EB1Z Evaluation Board user guide note,

1. It said charg pump setting 1 & 2 are 2.5mA, but PLL chip data sheet said Icp max=5.0mA using Rset=5.1K ohm.

Which one I should follow?

2.regarding to the phase detector polality, do I need to set it as Negative?

whereas Most of PLL chips are using Positive.

3. Actually, I am debuging my PLL circuit now, I think the output frequency is trying to lock.

But at that frequency, it is not quite lock to set frequency. I mean the output is slightly moving frequency, I tried to make the higher loop gain, as well as the lower loop band width, but it doen't work. I started the loop R, C values in my design from EV board recommanded values. Then, What are the next suggestions to work out this problem.

4. for debugging I am using the muxout, also. I would like to know the difference between digital  and alalog lock detect signal.

Pls, Help me, Thank you everyone.

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