I had several questions in regards to achieving deterministic latency for the jesd204 interface to the AD9136 or AD9144 DAC's over power cycles.
First could you get figures 57 and 59 replaced in the AD9136 data sheet pages 46 and 47 with the proper ones as now reflecting in the same sections of the AD9144 and AD9152 data sheets? Figures 57 and 58 of the link delay setup section in the AD9136 are totally incorrect for the examples, whereas the AD9144 and AD9152 data sheets are correct. I would be nice if these examples referenced the DAC JESD operational mode being used also....
I have at this point constructed a working demo design based with AD9136 FMC and Xilinx Zynq ZC706 under custom HDL and Linux drivers all based the ADI provided HDL and Linux driver basic builds for AD9144 using DAQ2 FMC.
The AD9136 setup is Mode 11 with 8 lanes all producing a nice pulse waveform from my custom subsystem with digital markers where the top JESD interface is ADI HDL and uses the ADI Linux JESD driver interface. Whereas I have custom AD9136 Linux driver based on AD9144 that setups up the AD9136 correctly.
Right now I have the AD9516 of the FMC card sending PECL 500MHz to the AD9136 DAC clock input with the VCO on to get 2GHz internal DAC clock. The AD9516 is generating the System Reference clocks also.
I tried to see if I could set the LMFC del and var registers up per the know link delay example given the Xilinx 6 and 7 JESD delays are the same. Since I am in Mode 11 using PClockFactor of 4 in calculation; but the AD9136 pulse waveform output has a non-deterministic latency of some range compared with my digital markers over power on cycles.
It is not clear from data sheets if I can get some level of deterministic latency when using the internal VCO of the AD9136.
In this regards what is requirement that the system reference clock fit around a setup and hold time of the DAC clock input?
What happens if the system reference clock does not met the internal VCO generated DAC clock setup and hold table 5 specs?
If the system reference is not aligned correctly to the DAC clock can setting the ERRWINDOW register 0X034 per table 42 make a difference in getting some level of overall deterministic latency of the JESD to DAC thru time period?
Should I look into skewing the AD9516 reference clock output phase to find a place the meets specs with the DAC clock timing?
If trying to use the link delay setup without know delay method page 33 and 47 to figuring out the LMFC del and var register values what should they be set to. The data sheet tables for setup for regs 0x304 to 0x0307 are blank referencing you back to the examples which said use the table values.
Should 0x304 and 0x305 be set to 0 and 0x306 and x0307 be set to 10dec/ 0x0a for the without know delay method power on cycle timing runs?
I realize the AD9136 and AD9144 FMC cards are used with the custom ADI wave generator boxes. I would be nice if one could see detailed register setups in regards to settings the AD9516 and DAC that are being used for the custom ADI wave generator boxes.
The whole subject of deterministic latency for ADI JESD DAC family really needs a detailed white paper that covers this area of design better with some good examples.