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ADF4355-2 Intermittent Lock of PLL

Question asked by brian2345 on Jan 15, 2016
Latest reply on Jan 22, 2016 by canberk_unal

Hello everyone,


Thank you for taking the time to read this posting.


I am working with an ADF4355-2 phased locked loop and I am experiencing issues with intermittent locking. Usually when I command the PLL to a certain frequency it will work, however about 5% of the time I cannot get the PLL to go to the right frequency.

I am using the PLL on a custom board that I designed.  I am using a microcontroller to write the registers on the PLL through the SPI port. I am using Analog Devices ADF4355…. Evaluation and Control software to set the correct register values, and then using its “Dump Register Contents” feature to send these registers to a file which then is sent to the microcontroller and then the PLL.  I am sending the PLL a 15.75 MHz reference clock, dividing this clock by 16 using the R counter, and then multiplying using INT to give frequencies in ~1MHz step from ~100MHz to ~1GHz.


Following is a list of some of the debugging steps that I have taken and observations that I have made.

  • - A literature search has found that analog devices had an intermittent issue with this part, the newest method is being used. See PCN 15_0018.
  • - Other posts on Engineer Zone have indicated intermittent lock issues such as this one,, the issue was resolved by using LE sync, which I am doing.
  • - I have tried setting muxout in register 4 to all possible combinations, the PLL only locks if muxout is set to the R or N dividers.  This is not a behavior that I would expect based on reading the data sheet.
  • - I have tried both the ADF4355 and ADF4355-2 and I see the same issue with both parts.
  • - I have tried two analog feedback loops, the one in the data sheet and one designed by ADIsimPLL 4.00.  I did not notice a difference between the two.
  • - I have tried adjusting numerous register options, and I still get the same result.
  • - I tried lengthening the timeouts in register 9 and lengthening the pause mention in the ADF4355-2 data sheet on page 29 under Frequency Update Sequence.  None of this seems to have helped.

I have attached a screen capture of the register configurations, note that this is just one of many configurations that I have tried.


I will appreciate all suggestions, hints, and observations.  Thank you.