We are using HMC700 to synthesize our 3rd LO(5.18-5.78GHz) in our L-band upconverter.
Reference oscillator is 10MHz OCXO with phase noise about -150dBc/Hz at 1kHz.
I initialize HMC700 writing strobe register(0x0, 0x0, 0x0, 0x2) to reset part to defaults,
charge pump register(0x13, 0xf8, 0x0, 0x0),PFD register(0x16, 0x0, 0x10, 0xfe), then
I write integer part register according to required frequency. I assume that after this initialization
part is integer mode. I obtain in-loop phase noise worse than calculates Hittite pll tool, but
it is enought to stay in specification.
The main problem is whan i write after all this fractional part lets say 0x8, 0x33,0x33,0x34(what
is equal about 1MHz). In-loop phase noise gets worse and i periodical spikes on carrier. Spikes
are similar to those i see from unshielded digital I/O. But nor in integer nor on secong pll-loop on same board
i dont see such spikes.
What can be reason of this spikes? Do phase noise in fractional mode worses by 10dB?