How to configure for an NMI on core1?
Having an NMI ISR on core0 was not a problem at all. The only thing was SEC_CCTL0 = 0x00010001. Worked fine. But to have it on core1 seems to be impossible ???
I disabled all possible settings on core0 and core1.
But when I run core1, generate an event on the NMI pin and check the SEC0_CSTAT1 register I can't see an NMI occurred. But I see it in SEC0_CSTAT0. And that while sec_cctl0 is completely cleared.
Does this mean an NMI can not be routed to core1?
When I study the ADSP-BF60x Blackfin Processor Hardware Reference page 7-11, it seems that the NMI path is not going through the SSI, but directly to the SCI.
That would mean SEC_CCTL1 = 0x00010001 should be enough to route the NMI event to the core. But no, nothing.
Isn't there a complete diagram of the SEC and the interrupt handling?
Because for example the location of GCTL and CSTAT is not shown in the manual right now.
In my case the CCES API is not an option. I need a bare metal solution.