AnsweredAssumed Answered

No-OS SW Reference design(AD9361) for Zedboard+AD-FMCOMMS2

Question asked by angleIsDancing on Jan 13, 2016
Latest reply on Mar 11, 2016 by DragosB

Hi,all,

    in the sw project, there is a line "dac_datasel(phy, -1, DATA_SEL_DMA) " at the end of the function dac_init()(in file dac_core.c )and according to the values of "dds_st[phy->id_no].pcore_version" and "chan" ,the function dac_datasel() will execute the for loop . at the end of the function dac_datasel(),there is a line "dds_st[phy->id_no].cached_datasel[chan] = sel"

 

the code snipped from the function dac_init()

====================================

  dac_dma_write(AXI_DMAC_REG_CTRL, 0);

  dac_dma_write(AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);

  dac_dma_write(AXI_DMAC_REG_SRC_ADDRESS, DAC_DDR_BASEADDR);

  dac_dma_write(AXI_DMAC_REG_SRC_STRIDE, 0x0);

  dac_dma_write(AXI_DMAC_REG_X_LENGTH, length - 1);

  dac_dma_write(AXI_DMAC_REG_Y_LENGTH, 0x0);

  dac_dma_write(AXI_DMAC_REG_START_TRANSFER, 0x1);

  dac_write(phy, DAC_REG_CNTRL_2, 0);

  dac_datasel(phy, -1, DATA_SEL_DMA);

===================================

 

the code snipped from the function dac_datasel()

==================================

if (chan < 0) { /* ALL */

  int i;

  for (i = 0; i < dds_st[phy->id_no].num_dds_channels; i++) {

  dac_write(phy, DAC_REG_CHAN_CNTRL_7(i), sel);

  }

  } else {

  dac_write(phy, DAC_REG_CHAN_CNTRL_7(chan), sel);

  }

(some other code)

dds_st[phy->id_no].cached_datasel[chan]=sel

====================================

my questions are:

1.the value of "chan" is -1, why it can be  a index of array.

2.what is the purpose of the for loop?  I  can understand it will set register 0x4418(reg_chan_cntrl_7)to 0x02(DMA) but what is the registers  0x4418+(i)*0x40(i from 1 to 7 ). I can't find them in Base (common to all cores) [Analog Devices Wiki]

 

do i misunderstand the program?

thanks,

gan.

Outcomes