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AD1974 Clock Signals

Question asked by TD1 on Jun 21, 2011
Latest reply on Jul 13, 2011 by TimW

The AD1974 ADC datasheet states the following in the Clock Signals section: "The on-chip PLL can be selected to reference the input sample rate from either the LRCLK or AUXCLRCLK pins or 256, 384, 512, or 768 times the sample rate, referenced to the 48 kHz mode from the MCLKI/XI pin."

 

Therefore, if I decide to use the 768 factor, does that not imply that I provide an input clock on the MCLKI/XI pin of 48 kHz x 768 = 36.864 MHz?  However the datasheet shows a maximum frequency of 13.8 MHz referencing the PLL mode with a 256 fs reference.  Am I to assume that the maximum frequency is scaled based on the multiplier?

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