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Frame based models are not supported for HDL code generation.

Question asked by diegonolovich on Jan 12, 2016
Latest reply on Jan 12, 2016 by ACozma

Hi - I am using one of your provided Simulink TX blocks with the most basic inputs as were included in the example file, just to learn the process of getting Simulink code running on the FPGA mesh. I hope to later use my more complex completed code converted to vhdl. I attach an image for reference. When I try to run HDL Coder to create a file I can get onto the FPGA board, I get the following error:

 

"Frame based models are not supported for HDL code generation."


If I set the samples per frame option on the Sine Wave and the ad9361_tx block to 1, I get no signal shown in my connected Spectrum Analyzer (SMA cable connected to the FMCOMMS3 CH1 TX port).


If I set the samples per frame on each of those blocks to 32768, then I get an output (though spurious).


How can I get the HDL Coder to work with the provided blocks?


bitfileTest_fail.PNG


Regards,

-Diego

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