There are a few threads on the issue of syncing the AD9129, and while there is good information on these threads I haven't been able to satisfactorily answered my question "can multiple AD9129's be synchronized without ambiguity across mutliple boards and maybe even different chassis". It looks like radial clocking schemes could be used to sync multiple FPGAs so that the DCI and FRAME are all aligned, but because of the DAC's internal divider it will still be necessary to align the SYNC signal on multiple boards using something like the XOR phase detector scheme referred to in figure 135 of the datasheet.
The thing that troubles me is the statement on the bottom of page 44 "By adjusting the internal delay (incrementing or decrementing by one DACCLK cycle with each write to Register 0x1A, Bit 7 or Bit 6, respectively), the user can align the DACCLKs inside the two DACs to within ±1 DACCLK cycle, when errors from the external phase detector, low-pass filter, and delay differences are taken
Does this imply that even with all the trouble of implementing hardware to do the phase detector I could still be a clock off? If this is so I don't see how this part could even be used in beam-forming applications etc. without a ton of calibration elsewhere in the system. Am I missing something?? Thanks so much.