I’m really new to hardware design. I have to implement an image processing system on a Xilinx zc702 due to a given task from my university.
I got the ADV7511 reference project runing and it's working well.
Now I intended to manipulate the image in the vdma with my own IP-Core doSobelHLS (a Sobel-Filter).
I've connected the M_AXIS_MM2S from vdma to my Input Stream of doSobelHLS and the output of doSobelHLS to the m_axis_mm2s of the axi_hdmi_tx.
After validating the design successfully and an init section in the SDK, unfortunately there’s nothing more than a black screen.
I have tried another IP-Core from Xilinx. But there are only white strips appearing on the screen.
Besides, I’ve also tried to connect the clock of doSobelHLS to the axi_clkgen and the FCLK_CLK0 of the PS.
Totally desperate now – I don’t know any more what else I can do or at what point I’m doing mistakes.
Can anyone please help me?
Please find the "hardware design and the init section" attached.