Hello

How much can we get the best phase noise floor at 1000MHz output?

REF input : 100MHz OCXO

VCO input : 1000MHz and a divider by 10

Phase detector: HMC439

Besr Regards,

yezhou

Hello

How much can we get the best phase noise floor at 1000MHz output?

REF input : 100MHz OCXO

VCO input : 1000MHz and a divider by 10

Phase detector: HMC439

Besr Regards,

yezhou

Hi David,

Thanks,

For most PLL, to calculate the noise floor at VCO out, using formula + 20logN+10logfPFD. How about HMC439?

For this case, if we use fPFD=200MHz or 50MHz, how much is the phase noise floor at 1000MHz output? The REF, Divider and Loop filter are assumed good enough.

Best Regards,

Yezhou

Hi Yezhou,

Yes, in general the HMC439 will follow the relationship of the formula which you cited. Although, we have not tested under those conditions, so it may be best for you to verify using your intended frequency, amplitude, waveform type. This is particularly the case for sine wave inputs. From the equation, one would assume the PFD floor would be lower with a lower REF frequency, but since it is slew rate dependent, then the floor may actually increase.

Best Regards,

David

Hi Yezhou,

The residual phase noise floor of the HMC439 will be dependent upon the input drive level and the rising edge of REF signal. A healthy 100MHz square waveform of +5dBm for the REF port will typically provide a residual phase noise floor of -153dBc/Hz. A low power sine wave of -10dBm would cause the residual noise floor to be much higher; approximately -135dBc/Hz.

For the PLL output of 1000MHz, you can calculate the phase noise of the intermediate offset frequencies (say 1kHz to the Loop BW cutoff), will be +20log(N=10) higher than the residual noise floor of the phase detector, or -133dBc/Hz. This assumes a healthy input REF signal and excludes any noise contributions from the dividers and loop filter.

Best Regards,

David