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ADV7611 output data not in sync incoming data

Question asked by Anil@Ren on Jan 8, 2016
Latest reply on Jan 18, 2016 by GuenterL

Hi,

 

We are generating a stable picture output and then sending it via HDMI output (TFP410PAP chip). When this is connected to a Monitor, we can observe the picture as intended. The resolution is 640x480@60p

 

Now using the above reference picture, we input this to ADV7611 chip. We expect ADV7611 to decode the incoming data and output it. Unfortunately, we observe that HYSNC, VSYNC, DE & LLC seem to be correct. But the Data is constantly changing. This implies that some how the incoming Data is not in sync with the outgoing data.

 

Attached are my setting

 

0x98, 0xFF, 0x80, //; I2C reset

0x98, 0xF4, 0x80, //; CEC

0x98, 0xF5, 0x7C, //; INFOFRAME

0x98, 0xF8, 0x4C, //; DPLL

0x98, 0xF9, 0x64, //; KSV

0x98, 0xFA, 0x6C, //; EDID

0x98, 0xFB, 0x68, //; HDMI

0x98, 0xFD, 0x44, //; CP

0x98, 0x01, 0x06, //; Prim_Mode =110b HDMI-GR

0x98, 0x02, 0xF2, //; Auto CSC, RGB out, dis op_656 bit

0x98, 0x03, 0x40, //; 24 bit SDR 444 Mode 0

0x98, 0x05, 0x28, //; AV Codes Off

0x98, 0x0B, 0x44, //; Power up part

0x98, 0x0C, 0x42, //; Power up part

0x98, 0x14, 0x7F, //; Max Drive Strength

0x98, 0x15, 0x80, //; Disable Tristate of Pins

0x98, 0x19, 0x83, //; LLC DLL phase

0x98, 0x33, 0x40, //; LLC DLL enable

0x44, 0xBA, 0x01, //; Set HDMI FreeRun

0x64, 0x40, 0x81, //; Disable HDCP 1.1 features

0x68, 0x9B, 0x03, //; ADI recommended setting

0x68, 0xC1, 0x01, //; ADI recommended setting

0x68, 0xC2, 0x01, //; ADI recommended setting

0x68, 0xC3, 0x01, //; ADI recommended setting

0x68, 0xC4, 0x01, //; ADI recommended setting

0x68, 0xC5, 0x01, //; ADI recommended setting

0x68, 0xC6, 0x01, //; ADI recommended setting

0x68, 0xC7, 0x01, //; ADI recommended setting

0x68, 0xC8, 0x01, //; ADI recommended setting

0x68, 0xC9, 0x01, //; ADI recommended setting

0x68, 0xCA, 0x01, //; ADI recommended setting

0x68, 0xCB, 0x01, //; ADI recommended setting

0x68, 0xCC, 0x01, //; ADI recommended setting

0x68, 0x00, 0x00, //; Set HDMI Input Port A

0x68, 0x83, 0xFE, //; Enable clock terminator for port A

0x68, 0x6F, 0x0C, //; ADI recommended setting

0x68, 0x85, 0x1F, //; ADI recommended setting

0x68, 0x87, 0x70, //; ADI recommended setting

0x68, 0x8D, 0x04, //; LFG

0x68, 0x8E, 0x1E, //; HFG

0x68, 0x1A, 0x8A, //; unmute audio

0x68, 0x57, 0xDA, //; ADI recommended setting

0x68, 0x58, 0x01, //; ADI recommended setting

0x68, 0x03, 0x98, //; DIS_I2C_ZERO_COMPR

0x68, 0x75, 0x10, //; DDC drive strength

 

For Debugging, i used the following information

I looked into the following and everything seems to be in line to my expectations:

0x98, 0x00, 0x08, // VGA 640x680@60

0x98, 0x01, 0x06, // HDMI-GR, 60Hz

 

0x68, 0x04, 0x23, // TMDS_PLL is locked to TDMS clock input

0x68, 0x05, 0x50, // HDMI Mode detected

0x68, 0x07, 0xA2, // Vertical filter locked, DE regeneration locked to incoming DE

0x68, 0x08,  0x80 // LineWidth 640

0x68, 0x09,  0x01 //

0x68, 0x0A, 0xE0 // Field0_Height 480

0x68, 0x0B, 0x01 // Progressive Input

0x68, 0x1C, 0x03 // FIFO has some margin, Video FIFO is not locked. Can this be some issue? How to solve this?


Any pointers into these issues would be great.


Regards,

Anil

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