I have used reference design project with KCU105 + ADFMCDAQ2_EBZ.
Bit file was successfully generated. Also I added ILA into the design and re-compiled.
I used this link for software
then I got some result from ILA as below
the signal at gt0-gt3_tx_charisk (4bit) looks like not working properly.
the data signal also doesn't look good.
I thought this reference design is working version.
Did I miss some procedure?
or Do I have to modify in SW code?
From my experience of JESD204B, this 4bit port need to be stable, not like this result.
if it keeps changes, it means it doesn't sync.
JESD204B IP send bcbcbcbc once they get "sync" or sysref (depends on subclass mode)
I have one more question.
If there is no input signal through GTX, I need to have loopback option to check internally.
However, there is no loopback port in block design of VIVADO.
I though JESD PHY(jesd9680) block has loopback , but there is no phy block either. (captured image below)
Is there another way to do loopback for JESD204B (to verify ADC/DAC internally)?
I appreciate any help or comment