In our application we are using AD9122 in a signal processing chain (feedback
system). It is critical to keep a constant phase of the signal with respect to
the reference after reset.
AD9122 is clocked directly from the reference clock (refCLK=101.28MHz), fed
with digital IQ data from an FPGA, and set up such that it modulates the input
IQ data by shifting them by the refCLK (so DC value on IQ data corresponds to
101.28MHz signal on the DAC output)
Unfortunately we noticed that after reset/reinitialization of the AD9122
registers the DAC output phase with respect to the reference ends up in one of
four positions (90deg shifts). After each initialization it falls into one of
these 4 phase states. How can we obtain a deterministic phase behavior after
reset? I can submit a complete register set if it helps. I did try to follow
multichip synchronization guide, but there must be something different or
misunderstood from my side, as it didn't change the situation.