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Successive conversions rising erroneously?

Question asked by IronMike on Jan 6, 2016
Latest reply on Jan 7, 2016 by IronMike

    I inherited a poor design that uses the ADuC834. fADC is 105 Hz. One aux channel, 16-bit sigma-delta converter, always shows an exponentially converging series [V0 * (1 - exp(-k * n)]  when N conversions are executed successively. The first measurement is the most accurate, and after 10 or so readings the value is erroneously high by about 100 counts.  I can interleave my measurements with other channels, and the artifact disappears, but I would like to take successive readings and average them.


  ** Why is this happening?  **

 

  I have no details on PCB construction or grounding.

 

  I have not verified if this happens on other channels.

 

  My setup:

  SF = 0x0D;

  ADC0CON = 0x47;

  ADC1CON = 0x70;

  ADCMODE = 0x31;

 

  Here is a typical series:  8099, 80bc, 80da, 80ea, 80f3, 80fd, 8100, 8107, 8109, 810b

 

  Thanks, Michael

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