AnsweredAssumed Answered

Changing AD9144 JESD204B IF Speed on FMCDAQ2

Question asked by castle on Jan 6, 2016
Latest reply on Feb 19, 2016 by rejeesh



Currently, I'm working with FMCDAQ2 board installed on KC705 Board. I use the reference design and working with 1GSPS DAC speed, no interpolation and 4x10Gbps line rate. With the default settings, everything is working fine. I'd like to change the JESD line rate down to 5Gbps. I changed the GTX TX Out Div. settings of the axi_daq2_gt IP core in order to get 5Gbps line rate and made the necessary changes in the AD9144 register settings. (2x interpolation, Serdes_pll_divFactor = 2, ENHALFRATE = 0) .

When I run the reference software all messages say everything is OK, but I couldn't get any output from the DAC.

I checked the link error monitoring registers and get these results:

0x470 = 0x0F

0x471 = 0x0F

0x472 = 0x00

0x473 = 0x00


It seems there is a checksum error in the link and ILAS is not achieved although K28.5 characters received on the lanes and frame sync is OK.

I think changing the Tx Out Div settings of the GTX is enough to change the line rate downto 5Gbps but should I change any other settings in the GTX (like QPLL settings, equalizer etc.), and/or in the AD9144?