I'm working on BF518F DSP (cclk: 400MHz, sysclk: 80MHz) using VDSP 5.0 update 9 and c-language.
I need to use 2 Timers (Timer0, Timer1) with this desired behaviour:
- Timer0 works at low frequency (around 50Hz) with 50% duty cycle, and it perform an ISR at the end of period
- Timer1 works faster (around 200 kHz) and it must shoot 20 pulses, with fixed frequency and duty cycle, starting at rising edge of Timer0: after 20 pulses it does stop.
So I start Timer1 within ISR of Timer0 (obviously starting from 2nd cycle of Timer0), but it always start 1us after rising edge of Timer0, and after this delay it works correctly.
Note that the start of Timer1 is the only operation (except the interrupt assertion) that I perform in Timer0 ISR.
Why this delay, bigger than the one explained in HWR manual (a few sysclk)?
Is there any way to exactly synchronize Timer1 start with rising edge of Timer0?
Thank you very much