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AD9102 register settings for QPSK modulation using its internal 4K buffer

Question asked by Bora on Jan 4, 2016
Latest reply on Jan 8, 2016 by Bora

Hi,

 

I plan to use AD9102 as QPSK modulator using its 4K x 14-bit internal RAM. First the QPSK data written to this internal buffer and then QPSK wave is generated by the AD9102 later for only once.

 

QPSK phase should change when output wave (Iout) crosses zero to reduce the spurs.

 

I will use internal VREF and operating voltage is 3.3V.

 

RSET is external and its value is 8.06 k. There is no automatic calibration.

 

My plan is to use it in standard 4-wire SPI interface, nCS, SDIO, SDO and SCLK. There is no double SPI. By the way, there is no detail for 3-wire SPI interface on its datasheet, how can we use it?

 

Output frequency may be 5 MHz, let the QPSK phase change in each new period (5 MSymbol/s or 10 Mbps rate).

 

It seems that there are 128 (0x00 – 0x7F) internal registers of AD9102 but a few of them are documented.

 

I have no demo board, I had never used LabView. As usual, I plan to program the DDS chip with a Blackfin DSP.

How can I generate a register file or can you send me an example file?

 

Change of phase on zero crossing or on the beginning of the period is very important.

 

Kind regards,

Bora

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