hi ADV7180 is not giving acknowledgement signal while reading and distorted ack while writing. i have implemented I2C protocol in FPGA virtex2P. SCK speed is 400 KHz. pl. advice
Did you try the setup using the ADI eval board?
no, i don't have the ADI EVAL board?. The following is the scope image of write cycle to ADV7180
the distorted pulse is the acknowledgement signal from ADV7180
For read cycle
n read cycle acknowledgement is generated by master (my vhdl program)
waiting for your reply
The design support files can be found at ADV7180 Design Support Files
Have you referred it?.
already i am having those files. can you give the details of I2C circuit in ADV7180
To added to Ramesh's and Jeyasudha's comments.
1) Try slowing the I2C bus down to 100kHz and see if this makes a difference. There could be something wrong in the timing at 400kHz or some board issue.
2) The blue SDA trace above with the value at mid point shows that something is driving the line high while something else is pulling the line low. I2C lines are open collector designs with pull up resistors only. There should be no case where the signal is driven to mid point and held there. Again this points to a possible problem with the FGPA driving the I2C bus.
Does any other I2C device work correctly on this I2C bus without out the SDA begin driven to the mid point?
Do you have another way to drive the I2C lines such as a USB to I2C adapter to check out it's functionality?
thanks Mr. GuenterL
actually i reduced the scK to 200 khz but, still the problem continues. sck rising time @ 400khz is approximately 190 nsec and the high and low periods are 1.2 usec each. i have used the 560 ohms pullup for sck and sda lines with vcc 3.3 volts. any problem in the waveform?
What is holding the SDA line at mid point? I2C lines should never hold at mid point especially if you have a 560 Ohm pull up. 2.2 - 4.7 KOhm resistors are normal pull up resistors.
Looking at the SDA line, it looks like the FPGA is driving the SDA line high while the ADV7180 is pulling it low giving you the mid point value. The FPGA SDA line should either be an input or a low output, never a high output.
in read cycle acknowledgement is generated by master (my vhdl program)
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