AnsweredAssumed Answered

ADAU1451 output port

Question asked by Sam.S on Dec 30, 2015
Latest reply on Jan 3, 2016 by Sam.S

Dear sir,

 

Our customer's project have four serial out from ADAU1451. OUT3 have independent BCLK/LRCK;

for layout board size and EMC concern, OUT1 and OUT2 share BCLK0/LRCK0 from OUT0 (PORT1 and PORT2 BCLK/LRCLK no layout, pin in open state).

 

Is any risk for this design?


Their class-D amp. not support TDM mode, so they can't use TDM mode design.


By the way, on SigmalStudio setting, they try to set SDATA_OUT1 and SDATA_OUT2 to:

LRCK: Slave from Clock domain 0

BCLK: Slave from Clock domain 0

and expect three OUT have synchronize clock.

 

But unfortunately SDATA_OUT1and SDATA_OUT2do not output data.


What time should set slave from other clock domain?


Thank you

and

Happy new year!!

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