The AD9467 needs a low jitter clock which generated by the AD9517-4. And the modifications has been made on the bord.It will work in the mode below,pll + internal vco.
So what will be changed in the code download from the GitHub?
We put in a 125MHz reference to generate a 250MHz output. Attached is the report and the python scripts used to configure the AD9517 for LVPECL and LVDS outputs.
I do not know how to modify the code for the AD9467-FMC-250EBZ. Here is the python code i used to setup the AD9517 on the AD9467-250EBZ (non FMC evb). The AD9517 is setup for LVDS outputs.
#import spi module
# setup spi
spi = ADCEval.ADCEval(1)
# set the Chip Select bit to 2
# short hand
swrite = spi.SPI_Write
#set chip to operate with 4 wire spi
swrite(0x017,0xB4) #PLL DLD Status register: 0x00 for gnd and 0x14 for PFD up pulse; B4 = DLD active high
swrite(0x018,0x07) #0x06 default and 0x07 VCO cal
swrite(0x01A,0x03) #LD register
swrite(0x01C,0x02) #Ref Select - select REF1 Default (0x02 for REF1 Power On)
swrite(0x0F5,0x0B) #Output 3 (PECL) 0x0B for PD, 0x08 for On
swrite(0x141,0x42) #Output 5 (LVDS) 0x43 for PD, 0x42 for On
# set transfer bit so changes take effect
Chipid = hex(ord(spi.SPI_Read(0x03)))
print "Chipid = ", Chipid
Status = hex(ord(spi.SPI_Read(0x017)))
print "Status = ", Status
LD_Status = hex(ord(spi.SPI_Read(0x01A)))
print "LD_Status = ", LD_Status
Thanks for sharing the design! It helps me a lot.
The ad9517 has been configured to generate a signal through the on-chip pll and vco. What is the frequency of the input clock to the REF1 and the output siganl frequency? The external loop filter has been modified? What frequency range of the default loop filter on the 9467fmc01c_sch.pdf from the ADI? How do you set the J300? If i want to generate a 200MHz sine signal through on-chip pll and vco while the input clock is 200MHz, how to set the vco divider and the loop filter?
Thank you! I know how to solve the problem!
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